full name / name of organization: 
Highly Efficient Accelerators and Reconfigurable Technologies


The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies
--HEART 2012--
Okinawa, Japan
May 31 - June 1, 2012

- Paper submission: February 21, 2012
- Author notification: March 26, 2012
- Camera-ready due: April 12, 2012
- Workshop date: May 31 - June 1, 2012

The 3rd International Workshop on Highly Efficient Accelerators and
Reconfigurable Technologies (HEART) is a forum to present and discuss
new research on accelerators and the use of reconfigurable
technologies for high-performance and/or power-efficient
computation. Submissions are solicited on a wide variety of topics
related to the acceleration for high-performance computation,
including but not limited to:

* Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA,
GPU, CELL/B.E and other devices
- Heterogeneous processors/systems for scalable, high-performance,
high-reliability and/or low-power computation
- Reconfigurable/configurable hardware and systems including
IP-cores, embedded systems, SoCs and cluster/grid/cloud computing
systems for scalable, high-performance and/or low-power processing
- High-performance custom-computing processors/systems
- Novel architectures and device technologies that can be applied to
efficient acceleration, including many-core architectures, NoC
architectures, 3D-stacking technologies and optical devices

* Software and applications:
- Novel applications for efficient acceleration systems/platforms,
and custom computing
- Compiler techniques and programming languages for efficient
acceleration systems/platforms, including many-core processors,
GPUs, FPGAs and other reconfigurable/custom processors
- Run-time techniques for acceleration, including Just-in-Time
compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous,
reconfigurable and/or custom processors/systems

In order to encourage open discussion on future directions, the
program committee will provide higher priority for papers that present
highly innovative and challenging ideas.

For more information, please visit .

Workshop Committees

Workshop Co-chairs:

- Hideharu Amano, Keio University, Japan
- Wayne Luk, Imperial College London, UK

Program Co-chairs:

- Walid Najjar, University of California Riverside, USA
- Yukinori Sato, JAIST, Japan
- David Thomas, Imperial College London, UK

Publication Co-chairs:

- Yuichiro Shibata, Nagasaki University, Japan
- Hironori Nakajo, Tokyo University of Agriculture and Technology, Japan

Publicity Co-chairs:

- Yoshiki Yamaguchi, University of Tsukuba, Japan
- Khaled Benkrid, the University of Edinburgh, UK
- Qiang Liu, Tianjin University, China

Finance Chair:

- Kentaro Sano, Tohoku University, Japan

Local Arrangement Chair:

- Yasunori Osana, University of Ryukyu, Japan

Design Contest co-chairs:
- Tomonori Izumi, Ritsumeikan University, Japan
- Minoru Watanabe, Shizuoka University, Japan